Knowledge and experience:

• We are looking for a broad scale of experience, but preferable you should have been working with UVM for at least one year
• Good understanding of UVM verification and SystemVerilog
• Used to work with complex ASIC and/or large FPGA design
• Experience from IP block verification
• Multi clock domains
• RTL within Verilog, VHDL and/or SystemVerilog
• Good English skills, in both speech and writing

Meritorious if you have:

• Test bench structuring and design
• Leadership qualities
• RTL design knowledge
• Scripting skills
• Lab experience
• Telecommunication

Location

Sweden\Stockholm